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32-macrocell max? epld cy7c344b cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03036 rev. *a revised december 28, 2002 44b features ? high-performance, high-density replacement for ttl, 74hc, and custom logic 32 macrocells, 64 expander product terms in one lab 8 dedicated inputs, 16 i/o pins advanced 0.65-micron cmos eprom technology to increase performance 28-pin, 300-mil dip, cerdip or 28-pin hlcc, plcc package functional description available in a 28-pin, 300-mil dip or windowed j-leaded ce- ramic chip carrier (hlcc), the cy7c344b represents the densest epld of this size. eight dedicated inputs and 16 bidi- rectional i/o pins communicate to one logic array block. in the cy7c344b lab there are 32 macrocells and 64 expander product terms. when an i/o macrocell is used as an input, two expanders are used to create an input path. even if all of the i/o pins are driven by macrocell registers, there are still 16 ? buried ? registers available. all inputs, macrocells, and i/o pins are interconnected within the lab. the speed and density of the cy7c344b makes it a natural for all types of applications. with just this one device, the de- signer can implement complex state machines, registered log- ic, and combinatorial ? glue ? logic, without using multiple chips. this architectural flexibility allows the cy7c344b to replace multichip ttl solutions, whether they are synchronous, asyn- chronous, combinatorial, or all three. max is a registered trademark of altera corporation. c344b ? 1 logic block diagram macrocell 2 macrocell 4 macrocell 6 macrocell 8 macrocell 10 macrocell 12 macrocell 14 macrocell 16 macrocell 18 macrocell 20 macrocell 22 macrocell 24 macrocell 26 macrocell 28 macrocell 30 macrocell 32 macrocell 1 macrocell 3 macrocell 5 macrocell 7 macrocell 9 macrocell 11 macrocell 13 macrocell 15 macrocell 17 macrocell 19 macrocell 21 macrocell 23 macrocell 25 macrocell 27 macrocell 29 macrocell 31 g l o b a l b u s i o c o n t r o l input input input input 15(22) 15(23) 27(6) 28(7) input 1(8) input/clk 2(9) input 13(20) input 14(21) i/o 3(10) i/o 4(11) i/o 5(12) i/o 6(13) i/o 9(16) i/o 10(17) i/o 11(18) i/o 12(19) i/o 17(24) i/o 18(25) i/o 19(26) i/o 20(27) i/o 23(2) i/o 24(3) i/o 25(4) i/o 26(5) 64 expander product term array 32 pin configurations top view hlcc 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 1516 1718 4 3 2 28 27 26 i/o i/o input input input i/o i/o input input input/clk i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o v cc 1 v cc input c344b ? 2 i/o gnd i/o i/o input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 input input top view cerdip input/clk i/o i/o i/o i/o v cc gnd i/o i/o i/o i/o input input input i/o i/o i/o i/o v cc gnd i/o i/o i/o i/o input input c344b ? 3 [1] selection guide 7c344b-15 7c344b-20 7c344b-25 maximum access time (ns) 15 20 25 note: 1. number in () refers to j-leaded packages.
cy7c344b document #: 38-03036 rev. *a page 2 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +135 c ambient temperature with power applied..............................................-65 c to +135 c maximum junction temperature (under bias)............. 150 c supply voltage to ground potential [2] ............ ? 2.0v to +7.0v dc output current, per pin [2] ................... ? 25 ma to +25 ma dc input voltage [2] ......................................... ? 2.0v to +7.0v operating range [3] range ambient temperature v cc commercial ? 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions min. max. unit v cc supply voltage maximum v cc rise time is 10 ms 4.75(4.5) 5.25(5.5) v v oh output high voltage i oh = ? 4.0 ma dc [4] 2.4 v v ol output low voltage i ol = 8 ma dc [4] 0.45 v v ih input high level 2.0 v cc +0.3 v v il input low level ? 0.3 0.8 v i ix input current gnd v in v cc ? 10 +10 a i oz output leakage current v o = v cc or gnd ? 40 +40 a t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance parameter description test conditions max. unit c in input capacitance v in = 0v, f = 1.0 mhz 10 pf c out output capacitance v out = 0v, f = 1.0 mhz 12 pf ac test loads and waveforms notes: 2. minimum dc input is ? 0.3v. during transactions, the inputs may undershoot to ? 2.0v or overshoot to 7.0v for input currents less then 100 ma and periods shorter than 20 ns. 3. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 4. the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jigand scope gnd 90% 10% 90% 10% 6 ns 6 ns 5v output r1 464 ? r2 250 ? (a) (b) output 1.75v equivalent to: th venin equivalent (commercial) c344b ? 5 c344b ? 6 all input pulses t f 5pf c344b ? 7 t r t f 163 ?
cy7c344b document #: 38-03036 rev. *a page 3 of 12 design recommendations operation of the devices described herein with conditions above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this data sheet is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. the cy7c344b contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid apply- ing any voltage higher than maximum rated voltages. for proper operation, input and output pins must be con- strained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be con- nected together directly at the device. power supply decou- pling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled. timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum ex- pander delay t exp to the overall delay. when calculating synchronous frequencies, use t su if all in- puts are on the input pins. when expander logic is used in the data path, add the appropriate maximum expander delay, t exp to t su . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t su ) is the lowest frequency. the lowest of these frequencies is the maximum data-path frequency for the synchronous con- figuration. when calculating external asynchronous frequencies, use t as1 if all inputs are on dedicated input pins. when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the low- est frequency. the lowest of these frequencies is the maxi- mum data-path frequency for the asynchronous configuration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive in- put hold times, which is controlled by the same synchronous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchro- nous clock under worst-case environmental and supply volt- age conditions. typical i cc vs. f max output drive current 240 180 120 60 1 khz 10 khz 100 khz 1 mhz i cc maximum frequency 10 mhz 0 50 mhz 100 hz active (ma) typ. v cc =5.0v room temp. c344b ? 8 01 2 3 4 i output current (ma) typical v o output voltage (v) 250 200 150 100 50 5 o i oh i ol v cc =5.0v room temp. c344b ? 9
cy7c344b document #: 38-03036 rev. *a page 4 of 12 figure 1. cy7c344b timing model logic array controldelay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in register output delay t od t xz t zx logic array delay t lad feedback delay t fd output input c344b ? 10 system clock delayt ics t rh t rsu t pre t clr i/o i/o delay t io i/o external synchronous switching characteristics over operating range 7c344b-15 7c344b-20 7c344b-25 parameter description min. max. min. max. min. max. unit t pd1 dedicated input to combinatorial output delay [5] com ? l/ind 15 20 25 ns t pd2 i/o input to combinatorial output delay [5] com ? l/ind 15 20 25 ns t su global clock set-up time com ? l/ind 9 12 15 ns t co1 synchronous clock input to output delay [5] com ? l/ind 10 12 15 ns t h input hold time from synchronous clock input com ? l/ind 0 0 0 ns t wh synchronous clock input high time com ? l/ind 6 7 8 ns t wl synchronous clock input low time com ? l/ind 6 7 8 ns f max maximum register toggle frequency [6] com ? l/ind 83.3 71.4 62.5 mhz t cnt minimum global clock period com ? l/ind 13 16 20 ns t odh output data hold time after clock com ? l/ind 1 1 1 ns f cnt maximum internal global clock frequency [7] com ? l/ind 76.9 62.5 50 mhz notes: 5. c1 = 35 pf 6. the f max values represent the highest frequency for pipeline data. 7. this parameter is measured with a 32-bit counter programmed into each lab.
cy7c344b document #: 38-03036 rev. *a page 5 of 12 external asynchronous switching characteristics over operating range 7c344b-15 7c344b-20 7c344b-25 parameter description min. max. min. max. min. max. unit t aco1 asynchronous clock input to output delay [5] com ? l/ind 15 18 22 ns t as1 dedicated input or feedback set-up time to asynchronous clock input com ? l/ind 5 6 8 ns t ah input hold time from asynchronous clock input com ? l/ind 5 6 8 ns t awh asynchronous clock input high time [8] com ? l/ind 6 7 9 ns t awl asynchronous clock input low time [8] com ? l/ind 7 9 11 ns t acnt minimum internal array clock frequency com ? l/ind 13 16 20 ns f acnt maximum internal array clock frequency [7] com ? l/ind 76.9 62.5 50 mhz typical internal switching characteristics over operating range 7c344b-15 7c344b-20 7c344b-25 parameter description min. max. min. max. min. max. unit t in dedicated input pad and buffer delay com ? l/ind 3 5 7 ns t io i/o input pad and buffer delay com ? l/ind 3 5 7 ns t exp expander array delay com ? l/ind 8 10 15 ns t lad logic array data delay com ? l/ind 7 10 13 ns t lac logic array control delay com ? l/ind 4 4 4 ns t od output buffer and pad delay [5] com ? l/ind 4 4 4 ns t zx output buffer enable delay [5] com ? l /ind 7 7 7 ns t xz output buffer disable delay [5] com ? l/ind 7 7 7 ns t rsu register set-up time relative to clock signal at register com ? l/ind 4 4 5 ns t rh register hold time relative to clock signal at register com ? l/ind 5 8 10 ns t latch flow-through latch delay com ? l/ind 1 1 1 ns t rd register delay com ? l/ind 1 1 1 ns t comb transparent mode delay com ? l/ind 1 1 1 ns t ic asynchronous clock logic delay com ? l/ind 7 8 10 ns t ics synchronous clock delay com ? l/ind 2 2 3 ns t fd feedback delay com ? l/ind 1 1 1 ns t pre asynchronous register preset time com ? l/ind 5 6 9 ns t clr asynchronous register clear time com ? l/ind 5 6 9 ns notes: 8. this parameter is measured with a positive-edge-triggered clock at the register. for the negative-edge clocking, the t ach and t acl parameter must be swapped.
cy7c344b document #: 38-03036 rev. *a page 6 of 12 switching waveforms external combinatorial dedicated input/ i/o input combinatorial output c344b-11 t pd1 /t pd2 c344b-12 t wl t su t h logic array t wh external synchronous clock at register synchronous synchronous logic array data from registered clock pin outputs t co1 external asynchronous t ah t as1 t awh t awl dedicated inputs or registered feedback c344b ? 13 asynchronous clock input c344b-14 t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd internal synchronous
cy7c344b document #: 38-03036 rev. *a page 7 of 12 switching waveforms (continued) internal combinatorial t in t exp t lac ,t lad c344b-15 t comb t od input pin i/o pin logic array logic array output input array delay expander output pin io t internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array c344b-16 t r
cy7c344b document #: 38-03036 rev. *a page 8 of 12 switching waveforms (continued) t in t ics t rsu t rh c344b-17 system cl ock pin system clock at register data from logic array internal synchronous ordering information speed (ns) ordering code package name package type operating range 15 cy7c344b-15hc/hi h64 28-lead windowed leaded chip carrier commercial/industrial cy7c344b-15jc/ji j64 28-lead plastic leaded chip carrier cy7c344b-15pc/pi p21 28-lead (300-mil) molded dip cy7c344b-15wc/wi w22 28-lead windowed cerdip 20 cy7c344b-20hc/hi h64 28-lead windowed leaded chip carrier commercial/industrial cy7c344b-20jc/ji j64 28-lead plastic leaded chip carrier cy7c344b-20pc/pi p21 28-lead (300-mil) molded dip cy7c344b-20wc/wi w22 28-lead windowed cerdip 25 cy7c344b-25hc/hi h64 28-lead windowed leaded chip carrier commercial/industrial cy7c344b-25jc/ji j64 28-lead plastic leaded chip carrier cy7c344b-25pc/pi p21 28-lead (300-mil) molded dip
cy7c344b document #: 38-03036 rev. *a page 9 of 12 package diagrams 28-pin windowed leaded chip carrier h64 51-80077
cy7c344b document #: 38-03036 rev. *a page 10 of 12 package diagrams (continued) 28-lead plastic leaded chip carrier j64 51-85001-a 51-85014-b 28-lead (300-mil) molded dip p21
cy7c344b document #: 38-03036 rev. *a page 11 of 12 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (300-mil) windowed cerdip w22 mil-std-1835 d-15 config. a 51-80087
cy7c344b document #: 38-03036 rev. *a page 12 of 12 document title: cy7c344b 32-macrocell max ? epld document number: 38-03036 rev. ecn no. issue date orig. of change description of change ** 106381 06/15/01 szv change from spec #: 38-00860 to 38-03036 *a 122235 12/28/02 rbi power up requirements added to operating range information

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